Efficient parallel cyclic redundancy check calculation using a novel table lookup approach

ABSTRACT

A system for cyclic redundancy check (CRC) calculations with modulo-2 multiplication is disclosed for repetitive CRC computations that optimizes processing efficiency and maximizes capacity. The resulting system results in the use of relatively fewer logical gates and conserves on power. The system receives a message ({right arrow over (m)}) including a plurality of blocks ({right arrow over (b)} i ) and a set of pre-computed coefficients ({right arrow over (β)} i ). The system performs a modulo-2 multiply-accumulate operation on the message ({right arrow over (m)}) using the relationship given by: 
     
       
         
           
             
               CRC 
                
               
                 ( 
                 
                   m 
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                 ) 
               
             
             ≡ 
             
               
                 CRC 
                 ( 
                 
                   
                     ∑ 
                     i 
                   
                    
                   
                     
                       
                         b 
                         → 
                       
                       i 
                     
                     ⊗ 
                     
                       
                         β 
                         → 
                       
                       i 
                     
                   
                 
                 ) 
               
               .

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to data processing systems and,more specifically, to systems and methods for optimizing the efficiencyand capacity of cyclic redundancy check operations.

BACKGROUND OF THE INVENTION

In current systems, parallel cyclic redundancy check (CRC) computationsinvolve decomposing an N-bit message into small blocks. Each block has afixed size (M). The fixed size typically equals the polynomial degree.Most approaches include computing the CRC of a message and performing aseries of N/M Galois multiply-accumulate operations. Each of the N/Mblocks is multiplied by a pre-stored coefficient, divided by the CRCpolynomial, and added to the accumulator. Accordingly, these systemsrequire N/M Galois parallel multiply-accumulate operations.

There are a number of disadvantages to such approaches. For example,Galois multipliers typically require the use of special hardware with aconsiderable number of logical gates. Conventional Galois multiplierarchitectures consume large areas of silicon. Moreover, Galoisoperations are rarely used in common applications. Furthermore, the CRCploynomial is typically hardwired into an efficient Galois multiplier.Such a design is not reconfigurable to support other polynomials.

There is therefore a need for a system and method that includes modulo-2multiplications for repetitive operations in CRC computations thatoptimize processing efficiency and maximize capacity.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure include a cyclic redundancy check(CRC) system with modulo-2 multiplications for repetitive CRCcomputations that optimize processing efficiency and maximize capacity.

In one embodiment, a method for cyclic redundancy checks (CRC) isdisclosed. The method includes receiving a message ({right arrow over(m)}). The message includes a plurality of blocks ({right arrow over(b)}_(i)) and a set of pre-computed coefficients ({right arrow over(β)}_(i)). The method also includes performing a modulo-2multiply-accumulate operation on the message ({right arrow over (m)}),wherein the operation is given by:

${{CRC}( \overset{arrow}{m} )} \equiv {{{CRC}( {\sum\limits_{i}{{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{\beta}}_{i}}} )}.}$

In another embodiment, a system for cyclic redundancy checks (CRC) isdisclosed. The system includes a controller capable of receiving amessage ({right arrow over (m)}). The message includes a plurality ofblocks ({right arrow over (b)}_(i)) and a set of pre-computedcoefficients ({right arrow over (β)}_(i)). The controller is alsocapable of performing a modulo-2 multiply-accumulate operation on themessage ({right arrow over (m)}). The operation is given by:

${{CRC}( \overset{arrow}{m} )} \equiv {{{CRC}( {\sum\limits_{i}{{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{\beta}}_{i}}} )}.}$

In still another embodiment, a process for cyclic redundancy checks(CRC) for use in a signal processing system is disclosed. The processincludes receiving a message ({right arrow over (m)}). The messageincludes a plurality of blocks ({right arrow over (b)}_(i)) and a set ofpre-computed coefficients ({right arrow over (β)}_(i)). The process alsoincludes performing modulo-2 multiply-accumulate operations on themessage ({right arrow over (m)}).

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, itmay be advantageous to set forth definitions of certain words andphrases used throughout this patent document: the terms “include” and“comprise,” as well as derivatives thereof, mean inclusion withoutlimitation; the term “or,” is inclusive, meaning and/or; the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with, becommunicable with, cooperate with, interleave, juxtapose, be proximateto, be bound to or with, have, have a property of, or the like; and theterms “element”, “construct” or “component” may mean any device, systemor part thereof that performs a processing, control or communicationoperation; and such a device may be implemented in hardware, firmware orsoftware, or some combination of at least two of the same. It should benoted that the functionality associated with any particular construct orcomponent may be centralized or distributed, whether locally orremotely. Definitions for certain words and phrases are providedthroughout this patent document, those of ordinary skill in the artshould understand that in many, if not most instances, such definitionsapply to prior, as well as future uses of such defined words andphrases.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure and itsadvantages, reference is now made to the following description taken inconjunction with the accompanying drawings, in which like referencenumerals represent like parts:

FIG. 1 illustrates a simplified block diagram of an exemplary digitalsignal processing system and controller for cyclic redundancy checkcalculations according to one embodiment of the present disclosure; and

FIG. 2 is a simplified flowchart illustrating a method in accordancewith one embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 and 2, discussed below, and the various embodiments used todescribe the principles of the present disclosure in this patentdocument are by way of illustration only, and should not be construed inany way to limit the scope of the disclosure. Hereinafter, certainaspects of the present disclosure are described in relation toillustrative embodiments and operations of wireless communicationssystems and networks. Those skilled in the art, however, will understandthat the principles and teachings of the present disclosure may beimplemented in a variety of suitably arranged signal processing systemsutilized in any number of end-equipment applications.

Typical Galois multiply-accumulate systems include a message ({rightarrow over (m)}) consisting of N bits. The message is a superposition ofa plurality of blocks ({right arrow over (b)}_(i)). Each block ({rightarrow over (b)}_(i)) is of a fixed size (e.g., M bits). The blocks aremultiplied over a Galois Field of prime two (e.g., GF(2)) with unitvectors ({right arrow over (e)}_(i)) shifted by M bits with respect toeach other. Thus, the message ({right arrow over (m)}) can be decomposedas shown by Equation 1 below:

$\begin{matrix}{\overset{\;arrow}{m} = {\sum\limits_{i = 0}^{{N/M} - 1}{{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{e}}_{i}}}} & \lbrack {{Eqn}.\mspace{14mu} 1} \rbrack\end{matrix}$

The summation and the multiplication operations included in Equation 1are performed over GF(2). The GF(2) multiplication is shown as thesymbol

while the GF(2) addition operation (an XOR operation) is shown as thesymbol “⊕”.

As an example of a typical application for Galois multiply-accumulatesystem, suppose a message ({right arrow over (m)}) containing sixteenbits (N=16) requires decomposition and is equal to the binary sequence[1101111100111010]. Suppose further that message ({right arrow over(m)}) is a superposition of blocks ({right arrow over (b)}_(i)) of afixed number of bits (M). For example, suppose M=4 and is equal to thepolynomial degree (or CRC width) W=3. Finally, suppose that the CRCpolynomial ({right arrow over (p)}) is equal to [1010].

In a typical Galois application, message ({right arrow over (m)}) isfirst divided into four blocks [{right arrow over (b)}₃ {right arrowover (b)}₂ {right arrow over (b)}₁ {right arrow over (b)}₀] of four bitseach, where {right arrow over (b)}₀=1010, {right arrow over (b)}₁=0011,{right arrow over (b)}₂=1111 and {right arrow over (b)}₃=1101. Moreover,message ({right arrow over (m)}) is the superposition of the blocks({right arrow over (b)}_(i)) multiplied by unit vectors ({right arrowover (e)}_(i)) as given in Equation 2 below:

{right arrow over (m)}={right arrow over (b)}₀

{right arrow over (e)}₀⊕{right arrow over (b)}₁

{right arrow over (e)}₁⊕{right arrow over (b)}₂

{right arrow over (e)}₂⊕{right arrow over (b)}₃

{right arrow over (e)}₃.   [Eqn. 2]

Continuing with the example above, suppose that the unit vectors ({rightarrow over (e)}_(i)) are given by {right arrow over (e)}₀=1, {rightarrow over (e)}₁=10000, {right arrow over (e)}₂=100000000 and {rightarrow over (e)}₃=1000000000000. Next, the CRC of the message ({rightarrow over (m)}) is given by the modulo-2 division of message ({rightarrow over (m)}) by the CRC polynomial ({right arrow over (p)}) as givenin Equation 3 below:

$\begin{matrix}{{{{CRC}( \overset{arrow}{m} )} \equiv {{CRC}( {\sum\limits_{i}{{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{e}}_{i}}} )}} = {\sum\limits_{i}{{{CRC}( {{\overset{arrow}{b}}_{i} \otimes ( {\overset{arrow}{e}}_{i} )} )}.}}} & \lbrack {{Eqn}.\mspace{14mu} 3} \rbrack\end{matrix}$

Using the modulation properties of Equations 4 and 5 below and afterassuming that x is smaller than p (i.e., mod(x)_(p)=x), Equation 3 maybe simplified to Equation 6 below, where {right arrow over(β)}_(i)≡CRC({right arrow over (e)}_(i)) and {right arrow over (β)}_(i)is a set of pre-computed coefficients:

$\begin{matrix}{{{{mod}( {x \oplus y} )}_{p} = {{{mod}(x)}_{p} \oplus \; {{mod}(y)}_{p}}};} & \lbrack {{Eqn}.\mspace{14mu} 4} \rbrack \\{{{{mod}( {x \otimes y} )}_{p} = {{mod}( {{{mod}(x)}_{p} \otimes {{mod}(y)}_{p}} )}_{p}};} & \lbrack {{Eqn}.\mspace{14mu} 5} \rbrack \\{{{CRC}( \overset{arrow}{m} )} \equiv {\sum\limits_{i}{{{CRC}( {{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{\beta}}_{i}} )}.}}} & \lbrack {{Eqn}.\mspace{14mu} 6} \rbrack\end{matrix}$

Finally, Equation 6 simplifies to Equation 7 below, where the CRCcalculation essentially becomes a series of Galois multiply-accumulateoperations:

$\begin{matrix}{{{CRC}( \overset{arrow}{m} )} \equiv {\sum\limits_{i}{{{gmpy}( {{\overset{arrow}{b}}_{i},{\overset{arrow}{\beta}}_{i}} )}.}}} & \lbrack {{Eqn}.\mspace{14mu} 7} \rbrack\end{matrix}$

In Equation 7, the blocks ({right arrow over (b)}_(i)) are of aparticular size (e.g., W bits or less).

FIG. 1 a simplified block diagram of a system 100 for cyclic redundancycheck calculations with modulo-2 multiplication in accordance with oneembodiment of the present disclosure. System 100 includes a digitalsignal processing system 101 having an input 102 and an output 103. Byway of example, system 100 may include wire line or wirelesscommunication devices (including cell phones, PCS handsets, personaldigital assistant (PDA) handsets, portable computers, telemetry devices,etc.), computer systems, audio and video equipment, satellitecommunications, multimedia applications, home automation systems and anyother systems requiring digital signal processing. Digital signalprocessing system 101 includes a controller 104 for performing cyclicredundancy check calculations according to one embodiment of the presentdisclosure. Digital signal processing system 101 may optionally includea lookup table 106. It should be understood that embodiments of thepresent disclosure may implemented into existing equipment, such asmultipliers.

In accordance with one embodiment of the present disclosure, however, aseries of modolu-2 multiply-accumulate operations is preferable. Inalternate embodiments, modulo-2 multiplications may be used for at leastsome of the repetitive operations performed in the cyclic redundancycheck (CRC) computations. As explained in greater detail below, a seriesof N-bit messages is parsed into blocks of size M for N/M parallelmodulo-2 and multiply-accumulate operations. Finally, the accumulator isdivided by the polynomial ({right arrow over (p)}).

As a specific example, Equation 3 above may be expanded using Equation 8to arrive at Equation 9 below.

$\begin{matrix}{{{mod}( {x \otimes y} )}_{p} = {{mod}( {{{mod}(x)}_{p} \otimes {{mod}(y)}_{p}} )}_{p}} & \lbrack {{Eqn}.\mspace{14mu} 8} \rbrack \\\begin{matrix}{{{CRC}( \overset{arrow}{m} )} = {\sum\limits_{i}{{CRC}( {{\overset{arrow}{b}}_{i} \otimes ( {\overset{arrow}{e}}_{i} )} )}}} \\{= {{CRC}( {\sum\limits_{i}{{CRC}( {{\overset{arrow}{b}}_{i}{\text{)} \otimes {\overset{arrow}{\beta}}_{i}}} )}} }}\end{matrix} & \lbrack {{Eqn}.\mspace{14mu} 9} \rbrack\end{matrix}$

Assuming that the block sizes ({right arrow over (b)}_(i)) are of size Wbits or less, Equation 9 may be further simplified to a series ofmodolu-2 multiply-accumulate operations, as shown in Equation 10:

$\begin{matrix}{{{CRC}( \overset{arrow}{m} )} \equiv {{CRC}( {\sum\limits_{i}{{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{\beta}}_{i}}} )}} & \lbrack {{Eqn}.\mspace{14mu} 10} \rbrack\end{matrix}$

The division operation by the CRC polynomial is an epilog operation.Therefore, processing speed becomes less essential and reconfigurabilitybecomes the main consideration.

FIG. 2 is a simplified flowchart illustrating method 200. Method 200provides a method for cyclic redundancy check (CRC) operations inaccordance with one embodiment of the present disclosure. Method 200begins with receiving a message ({right arrow over (m)}) from, forexample, input 102 of system 100 in step 201. The message includes aplurality of blocks ({right arrow over (b)}_(i)) and a set ofpre-computed coefficients ({right arrow over (β)}_(i)) In step 202,controller 104 performs a modulo-2 multiply-accumulate operation on themessage ({right arrow over (m)}) using the relationship given byEquation 10 above. Method 200 finally ends with step 203 by outputting asignal from digital signal processing system 101.

Embodiments of the present disclosure offer a number of advantages overpreviously known systems and methods. For example, the presentdisclosure is based on modulo-2 multiplications and therefore usesrelatively few logical gates and consumes less power when compared toprior art Galois multiplication techniques. Moreover, because themodulo-2 multiplication is not followed by a division, the operation maybe performed at higher clock speed than the prior art systems based onGalois multiplications.

Conventional Galois multiplication methods depend upon the polynomialsinvolved in the operation. As noted above, Galois multipliers havehardwired CRC polynomials and therefore are not reconfigurable tosupport other polynomials. Embodiments of the modulo-2 multiplicationoperation in accordance with the present disclosure, however, do notdepend on a specific polynomial. Moreover, a lookup table approach maybe implemented for full reconfigurability during polynomial divisionusing, for example, lookup table 106. Thus, the polynomial value may becustomized to suit a particular application.

Previous systems and methods require N/W CRC operations. According toone embodiment of the present disclosure, however, a series of GF(2)multiplications requires only one final CRC operation. Thus, oneembodiment of the present disclosure saves at least (N/W)-1 unnecessarydivisions.

Existing systems may be modified by turning off the carry bit capabilityand using the modulo-2 multiplication in accordance with the presentdisclosure. As another example, in one embodiment according to thepresent disclosure, the system and method may include performing thedivision of the accumulator by the CRC polynomial by a nibble usinglookup table 106. Lookup table 106 is preferably made up of 16×W bits.

Although certain aspects of the present disclosure have been describedin relation to specific systems, standards and structures, it should beeasily appreciated by one skilled in the art that embodiments of thesystem of the present disclosure provides and comprehends a wide arrayof variations and combinations easily adapted to a number of signalprocessing systems. As described herein, the relative arrangement andoperation of necessary functions may be provided in any manner suitablefor a particular application. All such variations and modifications arehereby comprehended. It should also be appreciated that the constituentmembers or components of this system may be produced or provided usingany suitable hardware, firmware, software, or combination(s) thereof.

The embodiments and examples set forth herein are therefore presented tobest explain the present disclosure and its practical application, andto thereby enable those skilled in the art to make and utilize thesystem of the present disclosure. The description as set forth herein istherefore not intended to be exhaustive or to limit any invention to aprecise form disclosed. As stated throughout, many modifications andvariations are possible in light of the above teaching without departingfrom the spirit and scope of the following claims.

1. A method for cyclic redundancy checks (CRC), comprising: receiving amessage ({right arrow over (m)}), wherein the message comprises aplurality of blocks ({right arrow over (b)}_(i)) and a set ofpre-computed coefficients ({right arrow over (β)}_(i)); and performing amodulo-2 multiply-accumulate operation on the message ({right arrow over(m)}), wherein the operation is given by:${{CRC}( \overset{arrow}{m} )} \equiv {{{CRC}( {\sum\limits_{i}{{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{\beta}}_{i}}} )}.}$2. The method of claim 1, wherein the coefficients ({right arrow over(β)}_(i)) are a function of a unit vector ({right arrow over (e)}_(i)).3. The method of claim 2, wherein the coefficients ({right arrow over(β)}_(i)) are given by:{right arrow over (β)}_(i)≡CRC({right arrow over (e)}_(i)).
 4. Themethod of claim 1, wherein the blocks ({right arrow over (b)}_(i)) areof a fixed number of bits (W).
 5. The method of claim 4 furthercomprising: reconfiguring a CRC polynomial using a lookup table.
 6. Themethod of claim 5, wherein the lookup table is made of 16×W bits.
 7. Themethod of claim 5, wherein reconfiguring the CRC polynomial isaccomplished by loading a new lookup table.
 8. A system for cyclicredundancy checks (CRC), comprising: a controller capable of: receivinga message ({right arrow over (m)}), wherein the message comprises aplurality of blocks ({right arrow over (b)}_(i)) and a set ofpre-computed coefficients ({right arrow over (β)}_(i)); and performing amodulo-2 multiply-accumulate operation on the message ({right arrow over(m)}), wherein the operation is given by:${{CRC}( \overset{arrow}{m} )} \equiv {{{CRC}( {\sum\limits_{i}{{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{\beta}}_{i}}} )}.}$9. The system of claim 8, wherein the coefficients ({right arrow over(β)}_(i)) are a function of a unit vector ({right arrow over (e)}_(i))10. The system of claim 9, wherein the coefficients ({right arrow over(β)}_(i)) are given by:{right arrow over (β)}_(i)≡CRC({right arrow over (e)}_(i)).
 11. Thesystem of claim 8, wherein the blocks ({right arrow over (b)}_(i)) areof a fixed number of bits (W).
 12. The system of claim 11 furthercomprising: a lookup table to aid in reconfiguring a CRC polynomial. 13.The system of claim 12, wherein the lookup table is made of 16×W bits.14. The system of claim 12, wherein the reconfiguring of the CRCpolynomial is accomplished by loading a new lookup table.
 15. For use ina signal processing system, a process for cyclic redundancy checks(CRC), comprising: receiving a message ({right arrow over (m)}), whereinthe message comprises a plurality of blocks ({right arrow over (b)}_(i))and a set of pre-computed coefficients ({right arrow over (β)}_(i)); andperforming modulo-2 multiply-accumulate operations on the message({right arrow over (m)}).
 16. The process of claim 15, wherein theoperations are given by:${{CRC}( \overset{arrow}{m} )} \equiv {{{CRC}( {\sum\limits_{i}{{\overset{arrow}{b}}_{i} \otimes {\overset{arrow}{\beta}}_{i}}} )}.}$17. The process of claim 15, wherein the coefficients ({right arrow over(β)}_(i)) are a function of a unit vector ({right arrow over (e)}_(i)).18. The process of claim 17, wherein the coefficients ({right arrow over(β)}_(i)) are given by:{right arrow over (β)}_(i)≡CRC({right arrow over (e)}_(i)).
 19. Theprocess of claim 15, wherein the blocks ({right arrow over (b)}_(i)) areof a fixed number of bits (W).
 20. The process of claim 19 furthercomprising: reconfiguring a CRC polynomial using a lookup table.
 21. Theprocess of claim 20, wherein the lookup table is made of 16×W bits. 22.The process of claim 20, wherein reconfiguring the CRC polynomial isaccomplished by loading a new lookup table.